Abstract:
Manufacturing advanced nodes (10nm and beyond) face significant challenges in pitch scaling and delivering better performance at iso power. Increased parasitics due to CPP and metal pitch scaling require significant innovation in patterning, conformal & higher aspect ratio filling and high selectivity atomic layer etching. Multi-pattern lithography with regularity and restrictive design rules have allowed us to move far beyond 193i capabilities. However, continued pitch scaling at advanced node will require EUV, at the least, on few critical layers. Innovation such as air gap is in not only a backend metal solution but also in frontend of processing to reduce parasitic capacitance and poses significant challenges in manufacturing. Advanced device architectures such as GAA nanowires transistors will further add their own set of manufacturing challenges at advanced nodes in terms of steeper dopant gradients and dopant activation requirements. In reality, industry will rise to these challenges with innovation and yet be pragmatic in choosing innovation that meets high volume manufacturing requirements.