Abstract:
Integrated Circuit scaling continues to see increasing complexities at increasing costs. The increasing complexities put economic pressure on technology advancements required for next generation integrated circuits. At the same time, these advances are required to meet the functionality needs of mobile computing, increased connectivity and high end servers. Essentially scaling will continue for increasing speed and density while striving for lower power and cost. In some ways we have passed the era where scaling is about packing more transistors on a die (Moore’s Law) and have transitioned to delivering the best performance per Watt for the desired application.
As the industry looks towards 5nm FinFET, it is approaching the theoretical limits of the FinFET due to channel width variations that could cause undesirable variability and mobility loss. Resistance and parasitic capacitance are dramatically increasing at each node and new technologies will be required to overcome this problem at the 5nm node. Trade-offs in drive current versus capacitance and power will pose a challenge o which channel materials to use. Parasitic effects like electro migration and thermal effects can increase as the FinFET is scaled down. There are other solutions being discussed for the 5nm node, such as Gate All Around FET, and SOI FinFETs, but for the purposes of this session we will focus on 5nm FinFETs although much of this discussion could be applied to other methods.
Electronic Design Automation, EDA, continues to develop models, methods and tools to help reduce time to market and costs, while increasing quality. EDA solutions can be utilized to help meet the challenges of scaling FinFET devices toward 5nm. To meet the challenges of 3D logic and memory devices, atomistic level features as well as new materials, the EDA industry has been developing 3D TCAD simulation capabilities, advanced compact models , and large capacity 3D field solver based parasitic extraction tools. The discussion topic of this presentation will focus on how 3D TCAD and 3D field solver based parasitic extraction tools can help improve time to market and reduce the cost for development of new technologies .