Network Synthesis Accelerates Impedance Matching Circuit Design
(Room 204)
18 Oct 18
2:40 PM
-
3:10 PM
Reducing product development time requires tools that support and expedite all stages of design, from translating performance requirements into an initial design through to optimization, physical realization and final verification all before fabrication and test. Addressing the initial stages of design through synthesis is an area of considerable interest to tool developers and designers alike. This is especially true for impedance matching circuits which are critical to the performance power amplifiers and other RF components found in communication system front-ends. Impedance matching becomes even more challenging as networks are required to operate over greater bandwidths to support LTE-A and 5G data capacities. This paper looks at advances in simulation optimization and network synthesis which have been developed specifically to support the design of impedance matching circuits. Complementing other developments in design automation and aids such as load-pull analysis, network synthesis accelerates design starts and allows designers to more fully explore design options through the creation of optimized two-port matching networks with discrete and distributed components based on user-defined performance goals.