EM Verification Within a Custom IC Design Platform
(Room 209)
18 Oct 18
1:40 PM
-
2:20 PM
To address 5G, IoT, ADAS, and other emerging applications, designers need a flow that spans early concept development through post-layout verification, integrating circuit simulation with RF system-level and mixed-signal baseband designs. While new, advanced nodes and shrinking packages are helping engineers meet the requirements for these applications, these technologies may also introduce RF interactions and parasitics that must be accounted for in the design. The verification of RF blocks within a single environment along with integrated EM analysis improves design cycle productivity, while reducing errors in manufacturing by accounting for the electrical and physical effects within a single environment across IC, package, and board design. To meet designers needs for a streamlined and comprehensive workflow, Cadence and NI have co-developed a bi-directional link that integrates key design technologies into a common user environment. The new Cadence® Virtuoso® RF Solution, which enables RF engineers to design, implement and analyze entire RF modules and RFICs using AXIEM 3D planar Method of Moments (MoM) EM simulation (from the NI AWR EDA software suite) within the Virtuoso custom IC design platform. This workshop introduces RFIC designers to this new interoperability, discussing the factors that are driving the need for EM simulation for analog silicon design, and some of the considerations for accurate EM analysis of on-chip passive components.