Practical Channel Modeling for High-speed Design
(Room Ballroom H)
17 Oct 18
5:35 PM
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6:05 PM
In the GB/s regime, accurate modeling of PCB interconnect is a precursor to successful high-speed serial link designs. In order to ensure first time success at these speeds, accurate channel modeling is a prerequisite. This is especially true for long backplane channels, or to meet industry standard chip to module specifications. Although many EDA tools include the latest and greatest models for conductor surface roughness and wideband dielectric properties, obtaining the right parameters to feed the models is always a challenge. So how do we get these parameters? Often the only sources are from data sheets alone. In most cases the numbers do not translate directly into parameters needed for the EDA tools. By using copper foil roughness and dielectric material properties, obtained solely from manufacturers’ data sheets, a practical method of modeling high-speed channels is presented.