Better Noise Characterization of Dynamic Comparators
(Room 209)
17 Oct 18
3:55 PM
-
4:35 PM
Dynamic comparators, often realized with Strong Arm latches, are used as the comparators in high speed, low power SAR Analog to Digital Converters. They are ideal for this application because they dissipate no static power while operating at high speed. These circuits are also used in as the decision circuits in SerDes so understanding their characteristics noise, et cetera is important. Unfortunately, these circuits operation is dynamic, and they don’t have quiescent operating points. As a result, traditionally SPICE small signal techniques, for example, ac analysis, can’t be used to analyze their performance and designers are forced to use transient analysis to analyze their behavior. We will look at analyzing the comparator noise with transient analysis, then introduce some enhancements to the standard transient noise analysis methodology that allow designers to understand the accuracy of the results. In addition, we will explore a methodology for performing small signal noise analysis of the comparator using periodic steady-state analysis. Other applications of periodic steady-state analysis based small signal analysis will be explored, for example, we will also look at the issue of how to simulate the comparator transfer function in order to derive the sampling aperture of the comparator. From these results some general guidelines for how to characterize dynamic comparators and how to simulate dynamic comparators integrated into circuits will be provided.