Concerns surrounding the appropriateness of Multicore Processors (MCPs) for safety-critical applications are well-established. Nevertheless, these processors offer significant advantages in terms of reduced Size, Weight, and Power (SWaP) consumption.
The task of accurately predicting Worst-Case Execution Times (WCET) for such devices is a current focal point within the avionics field. This challenge was succinctly captured in the CAST-32A document, and subsequently formalised in A(M)C 20-193. Even when dealing with a single core, determining WCET through static analysis alone can only yield an approximate result. But a different level of complexity is introduced when multiple cores come into play, because hardware shared resources (HSR) make any such static analysis impractical.
Despite CAST-32A & A(M)C 20-193 suggesting that the application of robust partitioning presents a solution to this conundrum, this paper will argue that while such an approach is beneficial, it cannot account for all HSRs and therefore cannot obviate the need to provide measured evidence that interference is adequately accounted for.
It will lead the reader through these ramifications, outlining a practical approach to achieving compliance with CAST-32A and A(M)C 20-193. This approach uses dynamic analysis and static analysis for interference analysis, supported by automated requirements traceability to effectively monitor these processes.