The rapid adoption of chiplet-based architectures for AI acceleration is redefining system complexity. Heterogeneous dies and ultra-fast UCIe/CoWoS interconnects deliver exceptional performance-per-watt, yet they also amplify exposure to process variation, thermal stress, accelerated aging, and dynamic, workload-induced voltage droop. Traditional pre-silicon sign-off alone can no longer guarantee field reliability or efficient bring-up.
In this joint submission, proteanTecs and Cadence present a holistic design-through-in-field methodology that embeds proteanTecs’ on-chip Agents into Cadence implementation and verification flows, creating self-monitoring Physical AI chiplet solutions.
Once deployed, embedded firmware and software applications running on the host SoC enable real-time insights and actions:
• Power reduction by dynamically reclaiming guard-bands to reduce voltage, with a reliability safety net
• Failure and SDC prevention through early detection of marginal timing under dynamic workloads and environmental conditions
• Accelerated RMA root-cause analysis in the field and with correlation to vendor production data
By extending Cadence’s chiplet platform with proteanTecs’ continuous in-field monitoring, we deliver a scalable path to resilient, energy-efficient Physical AI systems