Acceleration-Based Verification for UCIe: Overcoming Efficiency and Scale Limitations in Chiplet Interconnect Testing
(Room 303A)
05 Nov 25
3:25 PM
-
3:50 PM
The Universal Chiplet Interconnect Express (UCIe) standard represents a pivotal advancement in semiconductor integration, promising seamless, high-bandwidth communication among heterogeneous chiplets within a single package. However, this transformation also magnifies the challenges of ensuring correctness, compliance, and robust performance across ever-larger, more intricate multi-die designs. Its layered architecture and intricate protocol stacks introduce formidable verification challenges like High-Bandwidth Interface, Performance and Throughput limitations and sheer size of multi-die designs. Addressing these demands requires more than traditional simulation; it necessitates a shift toward accelerated hardware verification to manage the escalating complexity and performance expectations inherent to UCIe-based designs.
This paper presents a comprehensive analysis and verification environment design for acceleration-based platforms specifically tailored for UCIe connected systems. The Paper introduces methodology for verification of full stack as well as part-layer components compliant to UCIe protocol. It also introduces different topologies for covering chiplet level UCIe port verification as we as UCIe port network based multi-chiplet systems. The topologies also allow for system level verification through layering of software stimulus generation and control mechanism. In this paper, we elaborate on the benefits of our approach over traditional verification methodology.