As ASIC System-on-Chip (SoC) designs grow in complexity — driven by the demands of AI moving to the network edge, in automotive, industrial and consumer embedded applications — the network-on-chip (NoC) design has become a critical bottleneck. Firstly, a poor NoC design can throttle data flow through the device, crippling performance. Secondly, NoC implementation is traditionally a laborious manual task requiring highly specialized expertise. Inevitably, any design change will have an impact on the NoC, further delaying project timelines and consuming significant engineering resources. This talk explores how NoC automation, with constraint-driven topology generation and architectural reuse, is reshaping the way design teams approach NoC development for ASIC SoC designs.
We’ll examine real-world examples of how automation enables faster design-space exploration, improved responsiveness to floorplan and other design changes, all with better optimization of latency, wirelength, and power — all while reducing dependency on scarce NoC engineering expertise. Attendees will learn about emerging best practices in integrating smart generation techniques into existing SoC workflows and how this shift is influencing productivity, PPA outcomes, and team structures.
The session will offer practical insights for ASIC architects and SoC engineers seeking scalable approaches to interconnect design in increasingly heterogeneous systems.