Abstract:
Designing integrated circuits is an exercise in tradeoffs - how much circuitry should we put on a chip, what is the largest chip that remains economical, what circuit properties should we sacrifice in order to combine different technologies, what materials system should we choose, how should we conserve I/O structures, etc. Quilt Packaging (QP), conceived at the University of Notre Dame’s Center for Nano Science and Technology (NDnano), is a revolutionary new way for systems integrators to achieve on-chip performance without the cost and trade-offs of large, complex system-on-chip designs. QP offers the ability to combine multiple and disparate chip technologies into an array of chips, each one optimized for performance and cost, interconnected along their edges to form a "quilt" of chips that retains the full benefits of each component in one monolithic-like system.
To accomplish this, QP incorporates conductive “nodules” fabricated on the sides of chips to enable extremely wide bandwidth, low-loss electrical I/O, sub-micron mechanical chip-to-chip alignment, and chip-to-chip gaps as small as five microns. When utilized for electrical I/O, QP nodules perform as if they were on-chip interconnects even though they run off-chip and have demonstrated less than 1 dB of insertion loss across the entire bandwidth from 50 MHz to 220 GHz. The QP nodules are lithographically defined and fabricated in multiple, customizable geometries and can be functionally optimized for applications ranging from digital signal lines at 10 micron pitch, to “tuned” coplanar waveguides to power structures hundreds of microns wide.