SEMICON West 2016

FMC – Introducing a Scalable eNVM with Best in Class Power x Performance x Area (PPA)- Stefan Mueller, The Ferroelectric Memory Company (Room Innovation and IoT Theater, North Hall)

12 Jul 16
2:40 PM - 2:48 PM

Tracks: Silicon Innovation Forum

Abstract:

The Ferroelectric Memory Company – FMC has recently been established in order to solve one of the most important hardware challenges in the age of Internet-of-Things. Fabless companies as well as semiconductor manufacturers are nowadays looking for embedded nonvolatile memory solutions (eNVM) that enable products like microcontrollers (MCU) to follow Moore’s law. However, legacy eNVM solutions like eFlash cannot provide cost effective solutions that are so in need for the age of IoT. FMC commercializes a disruptive material innovation that will solve this problem for current and future technology nodes, i.e. eNVM based on ferroelectric hafnium oxide (FE-HfO2). The unexpected physical effect of ferroelectricity in HfO2 that has been discovered in Dresden, allows for the transformation of classical high-k metal-gate (HKMG) transistors into nonvolatile ferroelectric field effect transistors (FeFET). In this way, MCUs can easily be scaled from e.g. 65 nm down to 28 nm and beyond enabling tremendous advantages for the overall system: SoC cost reduction of around 80%, per bit write energy reduction by a factor of 1000 and an overall performance gain of the system of around 70% due to the transition to advanced process nodes. In terms of development status, the FeFET concept has already matured significantly. Single cell proof of principle has been demonstrated in 2012 and was transferred to 100 bit passive arrays in 2015. During the last months, first 64 Kbit active arrays have successfully been manufactured and characterized in close collaboration with the Dresden R&D consortium GLOBALFOUNDRIES, NaMLab gGmbH and Fraunhofer IPMS-CNT. First results will be presented at the Silicon Innovation Forum. Moreover, FMC has recently taped-out a 28 nm SoC prototype in collaboration with design partners RacyICs GmbH and Contronix GmbH that will enable the demonstration of a fully functional 28 nm SoC with 8 Mbit embedded FeFET memory by Q4/2016. Due to the close relation of FeFET and CMOS baseline, there is no roadblock for FMC’s technology to be applied also to alternative technology nodes like 22 nm FDSOI, 1X nm FinFET and beyond. FMC plans to enter into technology qualification by 2017 and is currently looking for Seed / Series A investment.