Selected "Attendee Choice" at BiTS 2016
Abstract:
Just how good is your high speed interconnect? The only way to know is to have an accurate characterization of its performance, and this can be a challenge when the interconnect is a pattern of small, flexible and conductive pins (Invisipin Conductive Elastomer) soldered to your PCB.
The Signal Integrity community has adopted S-parameters as the standard format to describe the performance of different elements of a signal path, such as traces, lumped capacitors, vias and interconnects. For multigigabit/s applications a time-domain representation needs to be derived from these S-parameter measurements in order to do Time Domain Analysis for impedance discontinuity or to create an eye diagram. For this time domain use, the S-parameters need to be set up correctly. Furthermore, if a probe station is not available for the 2-port S-parameter measurements, how do you “remove” the input and output connectors and various components in the PCB/Interconnect sandwich to provide only the contact performance?
This presentation will show how to isolate the interconnect performance taking into account the interaction of reflected signals as well as the series attenuation loss. Through VNA set-up, calibration, measurement/ assembly/re-measurement, and post-processing the pin’s isolated performance can be found.
With the versatility of Interconnect technology, there are a multitude of “pin” configurations that could be employed for your high speed signals. The location and number of ground contacts play a crucial role in the high speed performance. Having measured performance data for all possibilities would be time consuming. However, there is a way to be able to characterize your specific interconnect configuration: that would be to have an accurate 3D_EM model for the “pin” itself. Using a combination of measurements and HFSS, the 3D_EM simulator, an accurate model can be generated and then used to provide the predicted performance for your specific configuration.