Tracks: Extended Supply Chain Forum
Abstract:
The demand for next generation semiconductor devices is driving increased functional convergence as well as increased packaging complexity and sophistication. This is creating unprecedented demand for higher input/output (I/O) density, higher bandwidths and low power consumption while maintaining the cost structure of incumbent packaging technologies. JCET-Statschippac has developed several innovative solutions to address the needs of next generation Analog devices. These technologies enable a finer line and space to provide higher IO density in a smaller form factor. As a result, analog products can use advanced interconnect technologies in flip chip as well as wafer level packaging while meeting cost targets. Key technologies include fan out wafer level package (eWLB) and Molded Interconnect Substrate (MIS). These technologies can drive innovative packaging solutions in Analog devise and MEMS/sensors compared to traditional wirebond packaging. Some examples of such packaging solutions are shown.