2.5D/3D integration technology encompasses a wide variety of configurations which employ TSVs (Through Silicon/Substrate Vias) in a silicon wafer. 2.5D generally refers to heterogeneous integration of chips using interposers which typically have only passive components: wiring, capacitors and inductors. 3D technology goes beyond the interposer by integrating logic functionality in the assembly. 3D integration has the ability to enhance system performance by increasing bandwidth, reducing wire delay, and enabling better power management. In 3D technology, the TSVs may be integrated into the CMOS transistor fabrication at a number of points in the manufacturing sequence. Key considerations to determine the optimal introduction point include the size of the TSV, dimensional compatibility of the TSV with the BEOL (Back End Of Line) features, and the wiring design requirements. In this tutorial, we will review the various types of 2.5D and 3D integration, and why they offer significant advantages over conventional methods. We will also discuss the key elements of TSV fabrication including via etching, insulation, metallization, annealing, capping, as well as wafer grindside processing. We will also discuss the effects of TSVs on devices and BEOL structures, and the type of reliability testing that is required to evaluate the long-term impact of TSVs.
Presenter:
Mukta Farooq, Ph.D.
IEEE Fellow & IEEE EDS Distinguished Lecturer
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By June 3
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Starting June 4
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SEMI Member
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$50
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$50
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Non Member
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$75
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$75
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