Tracks: Advanced Manufacturing Forum - Track 2
Abstract:
Fins and wires — how do we get to 5nm?
Fundamental shifts are needed to address scaling challenges as the industry moves beyond 10nm to the 7nm and 5nm nodes. A priority concern driving changes in materials and architecture is the impact on transistor performance from rising parasitic resistance and parasitic capacitance. New materials challenges include cobalt for the contact as well as lower-k spacers and integration solutions such as air-gap and replacement contact schemes. 5nm appears to be the node where silicon and even the FinFET structure will not be thick enough to prevent quantum tunneling and gate leakage. Changes needed are new silicon germanium (SiGe) superlattices and a new transistor structure like gate all around (GAA) devices to fuel the next generation of device scaling.